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JS28F128P30BF75 - 128-Mbit Single Bit per Cell P30-65nm Flash Memory

Download the JS28F128P30BF75 datasheet PDF. This datasheet also covers the JS28F640P30BF75 variant, as both devices belong to the same 128-mbit single bit per cell p30-65nm flash memory family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High Performance:.
  • 65ns initial access time for Easy BGA and QUAD+.
  • 75ns initial access time for TSOP.
  • 25ns 8-word asynchronous-page read mode.
  • 52MHz with zero WAIT states, 17ns clock-todata output synchronous-burst read mode.
  • 4-, 8-, 16- and continuous-word options for burst mode.
  • 1.8V Low Power buffered programming at 1.8MByte/s (Typ) using 256-word buffer.
  • Buffered Enhanced Factory Programming at 3.2MByte/s (typ) using.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (JS28F640P30BF75-Numonyx.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number JS28F128P30BF75
Manufacturer Numonyx
File Size 1.07 MB
Description 128-Mbit Single Bit per Cell P30-65nm Flash Memory
Datasheet download datasheet JS28F128P30BF75 Datasheet

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Other Datasheets by Numonyx

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Numonyx® Axcell™ P30-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC) Datasheet Product Features „ High Performance: — 65ns initial access time for Easy BGA and QUAD+ — 75ns initial access time for TSOP — 25ns 8-word asynchronous-page read mode — 52MHz with zero WAIT states, 17ns clock-todata output synchronous-burst read mode — 4-, 8-, 16- and continuous-word options for burst mode — 1.8V Low Power buffered programming at 1.8MByte/s (Typ) using 256-word buffer — Buffered Enhanced Factory Programming at 3.2MByte/s (typ) using 256-word buffer „ Architecture: — Asymmetrically-blocked architecture — Four 32-KByte parameter blocks: top or bottom configuration — 128-KByte array blocks — Blank Check to verify an erased block „ Voltage and Power: — VCC (core) voltage: 1.7V – 2.