Datasheet4U Logo Datasheet4U.com

MC100EP139 - Clock Generation Chip

Datasheet Summary

Description

designed explicitly for low skew clock generation applications.

The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.

📥 Download Datasheet

Datasheet preview – MC100EP139

Datasheet Details

Part number MC100EP139
Manufacturer ON Semiconductor
File Size 197.79 KB
Description Clock Generation Chip
Datasheet download datasheet MC100EP139 Datasheet
Additional preview pages of the MC100EP139 datasheet.

📁 Similar Datasheet

  • MC100EP111 - LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL CLOCK DRIVER (Motorola)
  • MC100EP221 - LOW-VOLTAGE 1:20 DIFFERENTIAL ECL/PECL CLOCK DRIVER (Motorola)
  • MC100EP223 - Low Voltage 1:22 Differential PECL/HSTL Clock Driver (Motorola Semiconductor)
  • MC100E016 - 8-Bit Synchronous Binary Up Counter (Motorola)
  • MC100E101 - Quad 4-Input OR/NOR Gate (Motorola)
  • MC100E104 - QUINT 2-INPUT AND/NAND GATE (Motorola)
  • MC100E107 - QUINT 2-INPUT XOR/XNOR GATE (Motorola)
  • MC100E111 - 1:9 DIFFERENTIAL CLOCK DRIVER (Motorola)
  • MC100E112 - QUAD DRIVER (Motorola)
  • MC100E116 - QUINT DIFFERENTIAL LINE RECEIVER (Motorola)
Other Datasheets by ON Semiconductor

Full PDF Text Transcription

Click to expand full text
MC10EP139, MC100EP139 3.3 V / 5 V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control.
Published: |