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MC100LVEP210 - 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver

General Description

The MC100LVEP210 is a low skew 1 to

designed with clock distribution in mind.

ended if the VBB output is used.

The signal is fanned out to 5 identical differential outputs.

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Datasheet Details

Part number MC100LVEP210
Manufacturer onsemi
File Size 101.19 KB
Description 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver
Datasheet download datasheet MC100LVEP210 Datasheet

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Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode. The LVEP210 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 W even if only one output is being used.