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MC10E156 - 3-BIT 4:1 MUX-LATCH

Datasheet Summary

Description

The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs.

When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1).

Features

  • http://onsemi. com.
  • 950 ps Max. D to Output 850 ps Max. LEN to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC= 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 k.

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Datasheet Details

Part number MC10E156
Manufacturer ON Semiconductor
File Size 152.75 KB
Description 3-BIT 4:1 MUX-LATCH
Datasheet download datasheet MC10E156 Datasheet
Additional preview pages of the MC10E156 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com MC10E156, MC100E156 5V ECL 3-Bit 4:1 Mux-Latch Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. Features http://onsemi.com • • • • • • • • • • • • • • 950 ps Max. D to Output 850 ps Max. LEN to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables PECL Mode Operating Range: VCC = 4.2 V to 5.
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