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MC10E154 - 5-BIT 2:1 MUX-LATCH

Datasheet Summary

Description

The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs.

When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL.

Features

  • http://onsemi. com.
  • 850 ps Maximum LEN to Output 825 ps Maximum D to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model.

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Datasheet Details

Part number MC10E154
Manufacturer ON Semiconductor
File Size 153.06 KB
Description 5-BIT 2:1 MUX-LATCH
Datasheet download datasheet MC10E154 Datasheet
Additional preview pages of the MC10E154 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com MC10E154, MC100E154 5V ECL 5-Bit 2:1 Mux-Latch Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. Features http://onsemi.com • • • • • • • • • • • • • • 850 ps Maximum LEN to Output 825 ps Maximum D to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables PECL Mode Operating Range: VCC = 4.2 V to 5.
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