Overview: NB3H63143G 3.3 V / 2.5 V Programmable OmniClock Generator
with Single Ended (LVCMOS/LVTTL) and Differential (LVPECL/LVDS/ HCSL/CML) Outputs with Individual Output Enable and Individual VDDO .onsemi. The NB3H63143G, which is a member of the OmniClock family, is a one−time programmable (OTP), low power PLL−based clock generator that supports any output frequency from 8 kHz to 200 MHz. 1 The device accepts fundamental mode parallel resonant crystal or a QFN16 single ended (LVCMOS/LVTTL) reference clock as input. It CASE 485AE generates either three single ended (LVCMOS/LVTTL) outputs, or one single ended output and one differential MARKING DIAGRAM (LVPECL/LVDS/HCSL/CML) output. The output signals can be modulated using the spread spectrum feature of the PLL (programmable spread spectrum type, deviation and rate) for applications demanding low electromagnetic interference (EMI). Individual output enable pins OE[2:0] are available to enable/disable 3H631 43Gxx ALYWG
G the outputs. Individual output voltage pins VDDO[2:0] are available to independently set the output voltage of each output. Up to four 3H63143G = Specific Device Code xx = Specific Program Code (Default different configurations can be written into the device memory. Two selection pins (SEL[1:0]) allow the user to select the configuration to A use. Using the PLL bypass mode, it is possible to get a copy of the L Y input clock on any or all of the outputs. The device can be powered W down using the Power Down pin (PD#). It is possible to program the G ‘00’ for Unprogrammed Part) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package internal input crystal load capacitance and the output drive current provided by the device. The device also has automatic gain control (Note: Microdot may be in either location) (crystal power limiting) circuitry which avoids the device overdriving ORDERING INFORMATION the external crystal.
