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NB6L239 - 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider

Datasheet Summary

Description

The NB6L239 is a high

divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16.

Both divider circuits drive a pair of differential LVPECL outputs.

(More device information on page 7).

Features

  • Maximum Clock Input Frequency, 3.0 GHz.
  • CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL.
  • EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS.
  • Rise/Fall Time 65 ps Typical.
  • < 10 ps Typical Output.
  • to.
  • Output Skew.
  • Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz Outputs.
  • Internal 50 W Termination Provided.
  • Random Clock Jitter < 1 ps RMS.
  • QA B1 Edge Aligned to QBBn Edge.
  • Opera.

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Datasheet Details

Part number NB6L239
Manufacturer ON Semiconductor
File Size 143.52 KB
Description 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider
Datasheet download datasheet NB6L239 Datasheet
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Full PDF Text Transcription

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NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 7). The NB6L239 is a member of the ECLinPS MAX™ Family of the high performance clock products. Features • Maximum Clock Input Frequency, 3.0 GHz • CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL/HCSL • EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS • Rise/Fall Time 65 ps Typical • < 10 ps Typical Output−to−Output Skew • Example: 622.08 MHz Input Generates 38.88 MHz to 622.
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