NB6L295 - 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay

onsemi

Datasheet Details

Part number	NB6L295
Manufacturer	onsemi
File Size	180.92 KB
Description	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay
Datasheet	NB6L295 Datasheet

Other Datasheets by onsemi

Part Number	Description
NB6L295M	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay
NB6L239	2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider
NB6L11	2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL
NB6L11M	Differential CML Fanout Buffer
NB6L11S	Input to LVDS Fanout Buffer/Translator
NB6L14	Differential 1:4 LVPECL Fanout Buffer
NB6L14M	Differential 1:4 CML Fanout Buffer
NB6L14S	2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
NB6L16	6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential Lvecl Clock or Data Translator/receiver/driver Buffer
NB6L56	2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NB6L295 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs Multi−Level Inputs w/ Internal Termination The NB6L295 is a Dual Channel Programmable Delay Chip http://onsemi.com designed primarily for Clock or Data de−skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of two MARKING DIAGRAM* operating modes, a Dual Delay or an Extended Delay. 24 In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel.