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NB6L611 - Differential LVPECL Clock / Data Fanout Buffer

Datasheet Summary

Description

The NB6L611 is a differential 1:2 clock or data fanout buffer.

differential inputs incorporate internal 50 W termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels.

Features

  • Input Clock Frequency > 4.0 GHz.
  • 280 ps Typical Propagation Delay.
  • 100 ps Typical Rise and Fall Times.
  • 0.5 ps maximum RMS Clock Jitter.
  • Differential LVPECL Outputs, 780 mV Amplitude, typical.
  • LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V.
  • NECL Operating Range: VCC = 0 V with VEE =.
  • 2.375 V to.
  • 3.63 V.
  • Internal Input Termination Resistors, 50 W.
  • VREFAC Reference Output Voltage.

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Datasheet Details

Part number NB6L611
Manufacturer ON Semiconductor
File Size 269.40 KB
Description Differential LVPECL Clock / Data Fanout Buffer
Datasheet download datasheet NB6L611 Datasheet
Additional preview pages of the NB6L611 datasheet.

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Other Datasheets by ON Semiconductor
  • NB6L11 - 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL
  • NB6L11M - Differential CML Fanout Buffer
  • NB6L11S - Input to LVDS Fanout Buffer/Translator
  • NB6L14 - Differential 1:4 LVPECL Fanout Buffer
  • NB6L14M - Differential 1:4 CML Fanout Buffer
  • NB6L14S - 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
  • NB6L16 - 6GHz/6Gbps 2.5V/3.3V Multi-level Input to Differential Lvecl Clock or Data Translator/receiver/driver Buffer
  • NB6L239 - 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT Clock Divider

Full PDF Text Transcription

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NB6L611 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer Multi−Level Inputs with Internal Termination http://onsemi.com Description The NB6L611 is a differential 1:2 clock or data fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open.
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