NB6LQ572M Description
Each INx/INx input pair incorporates a fixed Equalizer Receiver, which when placed in series with a Clock / Data path, will enhance the degraded signal transmitted across an FR4 backplane or cable interconnect. For applications that do not require Equalization, consider the NB6L572M, which is pin −patible to the NB6LQ572M. The differential Clock / Data inputs have internal 50 W termination resistors and will accept...
NB6LQ572M Key Features
- 45 ps Typical Rise and Fall Times
- Differential CML Outputs, 400 mV Peak-to-Peak
- Typical GND = 0 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN-32 Package, 5mm x 5mm 40°C to +8
- Rev. 0