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NB6N14S - Differential Input to LVDS Fanout Buffer/Translator

Datasheet Summary

Description

Pin Name I/O Description 1 Q1 LVDS Output Non

inverted IN output.

Typically loaded with 100 W receiver termination resistor across differential pair.

Inverted IN output.

Features

  • Maximum Input Clock Frequency > 2.0 GHz.
  • Maximum Input Data Rate > 2.5 Gb/s.
  • 1 ps Maximum RMS Clock Jitter.
  • Typically 10 ps Data Dependent Jitter.
  • 380 ps Typical Propagation Delay.
  • 120 ps Typical Rise and Fall Times.
  • VREF_AC Reference Output.
  • TIA/EIA.
  • 644 Compliant.
  • Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices.
  • These are Pb.
  • Free Devices Device DDJ = 10 ps htt.

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Datasheet Details

Part number NB6N14S
Manufacturer ON Semiconductor
File Size 367.51 KB
Description Differential Input to LVDS Fanout Buffer/Translator
Datasheet download datasheet NB6N14S Datasheet
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Full PDF Text Transcription

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NB6N14S 3.3 V 1:4 AnyLevelt Differential Input to LVDS Fanout Buffer/Translator The NB6N14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevelt differential input signals: LVPECL, CML or LVDS. These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6N14S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6N14S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels.
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