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NB6N14S - Differential Input to LVDS Fanout Buffer/Translator

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ON Semiconductor

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NB6N14S Differential Input to LVDS Fanout Buffer/Translator by ON Semiconductor - Datasheet Preview — Datasheet preview – NB6N14S

Datasheet Details

Part number	NB6N14S
Manufacturer	ON Semiconductor
File Size	367.51 KB
Description	Differential Input to LVDS Fanout Buffer/Translator
Datasheet	NB6N14S Datasheet
Additional preview pages of the NB6N14S datasheet.

Product details

Description

Pin Name I/O Description 1 Q1 LVDS Output Non inverted IN output. inverted IN output.

Features

Maximum Input Clock Frequency > 2.0 GHz.
Maximum Input Data Rate > 2.5 Gb/s.
1 ps Maximum RMS Clock Jitter.
Typically 10 ps Data Dependent Jitter.
380 ps Typical Propagation Delay.
120 ps Typical Rise and Fall Times.
VREF_AC Reference Output.
TIA/EIA.
644 Compliant.
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices.
These are Pb.
Free Devices Device DDJ = 10 ps htt.

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Other Datasheets by ON Semiconductor

NB6N11S - Input to LVDS Fanout Buffer/Translator
NB6N239S - 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT Clock Divider
NB6HQ14M - 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
NB6L11 - 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL
NB6L11M - Differential CML Fanout Buffer
NB6L11S - Input to LVDS Fanout Buffer/Translator

Published: Apr 21, 2007 |