NB7L32M - Clock Divider w/CML Output and Internal Termination

Datasheet Summary

Description

inputs and asynchronous reset.

resistors and accept LVPECL (Positive ECL), CML, or LVDS.

The high frequency reset pin is asserted on the rising edge.

up,

Features

Maximum Input Clock Frequency 14 GHz Typical.
200 ps Max Propagation Delay.
30 ps Typical Rise and Fall Times.
< 0.5 ps Maximum (RMS) Random Clock Jitter.
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V.
CML Output Level (400 mV Peak.
to.
Peak Output), Differential Output Only.
50 W Internal Input and Output Termination Resistors.
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and.

ON Semiconductor

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Datasheet Details

Part number	NB7L32M
Manufacturer	ON Semiconductor
File Size	173.88 KB
Description	Clock Divider w/CML Output and Internal Termination
Datasheet	NB7L32M Datasheet
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Full PDF Text Transcription

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NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power−up, the internal flip−flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M’s in a system. The differential 16 mA CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated 50 W to VCC (See Figure 15). The device is housed in a small 3x3 mm 16 pin QFN package.

Published: Apr 23, 2007 |