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NLV74VHC1GT125 - Noninverting 3-State Buffer

Download the NLV74VHC1GT125 datasheet PDF. This datasheet also covers the NLV74VHC1G125 variant, as both devices belong to the same noninverting 3-state buffer family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Designed for 2.0 V to 5.5 V VCC Operation.
  • 3.5 ns tPD at 5 V (typ).
  • Inputs/Outputs Over.
  • Voltage Tolerant up to 5.5 V.
  • IOFF Supports Partial Power Down Protection.
  • Source/Sink 8 mA at 3.0 V.
  • Available in SC.
  • 88A, TSOP.
  • 5 and SOT.
  • 953 Packages.
  • Chip Complexity < 100 FETs.
  • NLV Prefix for Automotive and Other.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NLV74VHC1G125-ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for NLV74VHC1GT125 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NLV74VHC1GT125. For precise diagrams, and layout, please refer to the original PDF.

Noninverting 3-State Buffer NLV74VHC1G125, NLV74VHC1GT125 The NLV74VHC1G125 / NLV74VHC1GT125 is a single non−inverting 3−state buffer in tiny footprint packages. The NLV7...

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ngle non−inverting 3−state buffer in tiny footprint packages. The NLV74VHC1G125 has CMOS−level input thresholds while the NLV74VHC1GT125 has TTL−level input thresholds. The internal circuit is composed of three stages, including a buffered 3−state output which provides high noise immunity and stable output. The input structures provide protection when voltages up to 5.5 V are applied, regardless of the supply voltage. This allows the device to be used to interface 5 V circuits to 3 V circuits. Some output structures also provide protection when VCC = 0 V and when the output voltage exceeds VCC.