Datasheet Summary
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop
The SN74LS109A consists of two high speed pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. http://onsemi.
MODE SELECT
- TRUTH TABLE
INPUTS OPERATING MODE SD Set Reset (Clear)
- Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset)
- L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H H q q L Q L H H L q q H OUTPUTS
LOW POWER SCHOTTKY
16 1
Both outputs will be HIGH while both SD and CD are LOW, but the output states are...
