SN74LS109A Description
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.
SN74LS109A Key Features
- h q q HHh
- q q HH
- l LH * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD