SN74LS109A Datasheet | Motorola Semiconductor

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12) J 2(14) K 3(13) Q 6(10) Q 7(9) MODE SELECT - TRUTH TABLE OPERATING MODE INPUTS SD CD J OUTPUTS KQQ Set Reset (Clear) - Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) LHXXHL HLXXLH L L XXHH HHh hHL HH l h q q HHh l q q HH l l LH - Both outputs will be HIGH while both SD and CD are LOW, but...