Datasheet Summary
Dual JK Positive Edge- Triggered Flip- Flop
The SN74LS109A consists of two high speed pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together.
MODE SELECT
- TRUTH TABLE
OPERATING MODE
INPUTS
SD CD
OUTPUTS
Set Reset (Clear)
- Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset)
H h h
H l h q q
H h l q q
H l l
- Both outputs will be HIGH while both SD and CD are LOW, but the output states are...
