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SN74LS107A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Download the SN74LS107A datasheet PDF. This datasheet also covers the SN74LS107N variant, as both devices belong to the same dual jk negative edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (SN74LS107N_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
SN74LS107A DUAL J-K FLIP-FLOPS Texas Instruments
SN74LS10 TRIPLE 3-INPUT POSITIVE-NAND GATES Texas Instruments
SN74LS10 TRIPLE 3-INPUT NAND GATE ON Semiconductor
SN74LS109 LOW POWER SCHOTTKY ON Semiconductor
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop ON Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
SN74LS10 TRIPLE 3-INPUT NAND GATE
SN74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS11 TRIPLE 3-INPUT AND GATE
SN74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner power pins. SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC CD1 CP1 14 13 12 K2 11 CD2 CP2 10 9 J2 8 1234567 J1 Q1 Q1 K1 Q2 Q2 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.