The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs.
The Clock (CP) and Master Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW to HIGH Clock (CP) transition.
| Part number | SN74LS174 |
|---|---|
| Manufacturer | onsemi |
| File Size | 178.06 KB |
| Description | Hex D Flip-Flop |
| Datasheet |
 SN74LS174 Datasheet
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Note: Below is a high-fidelity text extraction (approx. 800 characters) for SN74LS174. For precise diagrams, and layout, please refer to the original PDF.
SN74LS174 Hex D Flip−Flop The LSTTL/MSI SN74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The informatio...
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
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SN74LS174 | HEX D FLIP-FLOP | Motorola |
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SN74LS174 | HEX/QUADRUPLE D-TYPE FLIP-FLOPS | Texas Instruments |
| Part Number | Description |
|---|---|
| SN74LS175 | Quad D Flip-Flop |
| SN74LS10 | TRIPLE 3-INPUT NAND GATE |
| SN74LS109 | LOW POWER SCHOTTKY |
| SN74LS109A | Dual JK Positive Edge-Triggered Flip-Flop |
| SN74LS122 | Retriggerable Monostable Multivibrator |
| SN74LS123 | Retriggerable Monostable Multivibrator |
| SN74LS125A | Quad 3-State Buffer |
| SN74LS126A | Quad 3-State Buffer |
| SN74LS132 | Quad 2-Input Schmitt Trigger NAND Gate |
| SN74LS138 | 1-of-8 Decoder/Demultiplexer |
