Download the SN74LS173A datasheet PDF.
This datasheet also covers the SN74LS173D variant, as both devices belong to the same 4-bit d-type register family and are provided as variant models within a single manufacturer datasheet.
Full PDF Text Transcription for SN74LS173A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
SN74LS173A. For precise diagrams, and layout, please refer to the original PDF.
4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. The clock is ful...
View more extracted text
ing 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either Output Enable line (OE1, OE2) brings the output to a high impedance state without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines.
SN74LS173A Datasheet
