NB6VQ572M Description
Each INx / INx input pair incorporates a fixed Equalizer Receiver, which when placed in series with a Clock / Data path, will enhance the degraded signal transmitted across an FR4 backplane or cable interconnect. For applications that do not require Equalization, consider the NB7V572M, which is pin −patible to the NB6VQ572M. The differential Clock / Data inputs have internal 50 W termination resistors and will...
NB6VQ572M Key Features
- Differential CML Outputs, 400 mV Peak-to-Peak
- Rev. 0