PM5315 Datasheet | PMC-Sierra

FEATURES - Monolithic SONET/SDH Payload Extractor/Aligner for use in interface applications, operating at serial interface speeds of up to 2488 Mbit/s: - single STS-48c (STM-16/AU4-16c); - single STS-48 (STM-16/AU44c/AU4/AU3/TU3); - quad STS-12c (STM-4/AU4-4c); - quad STS-12 (STM4/AU4/AU3/TU3). - In single STS-48/STM-16 mode, supports a duplex 16-bit 155.52 MHz differential PECL line side interface for direct connection to external clock recovery, clock synthesis and serializer-deserializer ponents. - In quad STS-12/STM-4 mode, supports four duplex 8-bit 77.76 MHz TTL patible line side interfaces for direct connection to external clock recovery, clock synthesis and serializer-deserializer ponents. - Provides termination for SONET Section, Line and Path overhead or SDH Regenerator Section, Multiplexer Section and High Order Path overhead. - In single STS-48/STM-16 mode provides a 32-bit 77.76 MHz ADD and DROP Tele Bus. - In quad STS-12/STM-4 mode provides four 8-bit 77.76 MHz ADD and DROP Tele Bus Interfaces. - Maps SONET/SDH payloads to system timing, acmodating plesiochronous timing offsets between the line and system timing references, through pointer processing. - The entire SONET/SDH transport and path overheads are extracted to and inserted from dedicated pins. - Frames to the SONET/SDH receive stream and inserts framing bytes and STS identification into the transmit stream and processes or inserts the transport overhead. - Interprets or generates the STS (AU) pointer bytes (H1, H2, H3), extracts or inserts the synchronous payload envelope(s) and processes or inserts the path overhead. - Provides Time Slot Interchange (TSI) function at the ADD and DROP Tele Bus Interfaces for grooming any legal mix of SONET/SDH paths. - Supports Automatic Protection Switching (APS): - Ring control port munication of path REI and path RDI alarms; - Filters the APS channel (K1,K2) bytes into internal registers; inserts the APS channel into the transmit stream. - Supports line...