PYA28C64 Datasheet | PYRAMID

FEATURES Access Times of 150, 200, 250 and 350ns Single 5V±10% Power Supply Fast Byte Write (200µs or 1 ms) Low Power CMOS: - 60 m A Active Current - 150 µA Standby Current Fast Write Cycle Time RDY/BUSY pin is not connected for the PYA28C64X PYA28C64(X) 8K X 8 EEPROM CMOS & TTL patible Inputs and Outputs Endurance: - 10,000 Write Cycles - 100,000 Write Cycles (optional) Data Retention: 10 Years Available in the following package: - 28-Pin 600 mil Ceramic DIP - 32-Pin Ceramic LCC (450x550 mils) DESCRIPTION The PYA28C64 is a 5 Volt 8Kx8 EEPROM. The PYA28C64 features DATA and RDY/BUSY (PYA28C64 only) to indicate early pletion of a Write Cycle. Data Retention is 10 Years. The device is available in a 28-Pin 600 mil wide Ceramic DIP and 32-Pin LCC. PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM DIP (C5-1) Document # EEPROM105 REV B LCC (L6) NOTE: The RDY/BUSY pin is not connected for the PYA28C64X. Revised June 2012 - 8K x 8 EEPROM OPERATION READ Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. BYTE WRITE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PYA28C64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to pletion. CHIP CLEAR The contents of the entire memory of the PYA28C64 may be set to the high state by the CHIP CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low pulse is applied to WE. DEVICE IDENTIFICATION An extra 32 bytes of EEPROM memory are...