Overview: CCD Delay Line Series MN3867S
PAL-patible CCD Video Signal Delay Element
Overview
The MN3867S is a CCD signal delay element for video signal processing applications. It contains such ponents as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 1700 and 617 stages and between 848.5 and 617 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38667S samples the input using the supplied clock signal with a frequency three times the PAL color signal subcarrier frequency (4.43361875 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) and 2 H for the two lines. When the switch input is "H" level, the MN38667S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.65625 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC VSS3 VDD3 VINC1 N.C.
