Datasheet4U Logo Datasheet4U.com

PI6C2405A - Zero-Delay Clock Buffer

General Description

The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V.

All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL.

Key Features

  • Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 300ps Internal feedback allows outputs to be synchronized to the clock input 5V tolerant input.
  • Spread spectrum clock ready Operates at 3.3V VDD Packaging (Pb-free & Green available): -8-pin, 150-mil SOIC (W) -8-pin, 173-mil TSSOP (L).

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PI6C2401 Phase-Locked Loop Clock Driver Pericom Semiconductor
PI6C2404A-1 Zero-Delay Clock Buffer Pericom Semiconductor
PI6C2501 Phase-Locked Loop Clock Driver Pericom Semiconductor
PI6C2504 Phase-Locked Loop Clock Driver Pericom Semiconductor
PI6C2952 Low Voltage PLL Clock Driver Pericom Semiconductor

Other Datasheets by Pericom Semiconductor (now Diodes Incorporated)

Part Number Description
PI6C2408 3.3V 4+4 Ouptut Zero-delay Clock Driver
PI6C2409 Zero-Delay Clock Buffer
PI6C2502 Phase-Locked Loop Clock Driver
PI6C2502A Phase-Locked Loop Clock Driver
PI6C2510-133 Low-Noise/ Phase-Locked Loop Clock Driver with 10 Clock Outputs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PI6C2405A Zero-Delay Clock Buffer Features • • • • • • • • Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 300ps Internal feedback allows outputs to be synchronized to the clock input 5V tolerant input* Spread spectrum clock ready Operates at 3.3V VDD Packaging (Pb-free & Green available): -8-pin, 150-mil SOIC (W) -8-pin, 173-mil TSSOP (L) Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL.