PI6C39911 Datasheet | Pericom Semiconductor

Features - All output pair skew <100ps typical (250 Max.) - 12.5 MHz to 133 MHz output operation - 3.125 MHz to 133 MHz input operation (input as low as 3.125 MHz for 4x operation, or 6.25 MHz for 2x operation) - User-selectable output functions - Selectable skew to 18ns - Inverted and non-inverted - Operation at ½ and ¼ input frequency - Operation at 2X and 4X input frequency - Zero input-to-output delay - 50% duty-cycle outputs - Inputs are 5V Tolerant - LVTTL outputs drive 50-Ohm terminated lines - Operates from a single 3.3V supply - Low operating current - 32-pin PLCC package - Jitter < 200ps peak-to-peak (< 25ps RMS) Description The PI6C39911 offers selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance puter systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50-Ohms while delivering minimal and specified output skews and full-swing logic levels. Each output can be hardwired to one of nine skews or function configurations. Delay increments of 0.7ns to 1.5ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The pletely integrated PLL allows external load and transmission line delay effects to be canceled. The user can create output-to-output skew of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing plex clock systems. When bined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature allows flexibility and simplifies system timing distribution design for plex high-speed systems. Logic Block Diagram Test FB REF FS 4F0 4F1 Select Inputs (three level) Pin...