PI6CU877 Datasheet | Pericom Semiconductor

Features - PLL clock distribution optimized for DDR2 SDRAM applications. - Distributes one differential clock input pair to ten differential clock output pairs. - Differential .. Inputs (CLK, CLK) and (FBIN, FBIN) - Input OE/OS: LVCMOS - Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT) - External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. - Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers - Packaging (Pb-free & Green available): - 52-ball VFBGA (NF) Description PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to eleven differential pairs of clock outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT, FBOUT). The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is LOW the outputs except FBOUT, FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS is a program pin that must be tied to GND or VDD. When OS is high, OE will function as described above. When OS is LOW, OE has no effect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When CLK/CLK are logic low, the device will enter a low power mode. An input logic detection circuit will detect the logic low level and perform a low power state where all Y[0:9], Y[0:9]; FBOUT, FBOUT, and PLL are OFF. 3 Y0 GND NB VDDQ NB NB VDDQ NB GND Y4 Pin Configuration 1 A B C D E F G H J k Y1 Y1 Y2 Y2 CK CK AGND AVDD Y3 Y3 Y0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND Y4 Y5 GND NB VDDQ NB NB VDDQ NB GND Y9 Y5 GND GND OS VDDQ OE VDDQ GND GND Y9 Y6 Y6 Y7 Y7 FBIN FBIN FBOUT FBOUT Y8 Y8 PI6CU877 is a high performance, low skew, and low jitter PLL clock driver, and it is...