PI6CV857B Description
PI6CV857B PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT,FBOUT) . The...
PI6CV857B Key Features
- Operating Frequency up to 200 MHz and exceeds PC2700 RDIMM specification
- Distributes one differential clock input pair to ten differential clock output pairs
- Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
- Input PWRDWN: LVCMOS
- Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
- External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input
- Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers
- Packages (Pb-free and Green available)
- 48-pin TSSOP