Description
PI6CV857B PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels.
Features
- Operating Frequency up to 200 MHz and exceeds PC2700 RDIMM specification.
- Distributes one differential clock input pair to ten differential clock output pairs.
- Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 www. DataSheet4U. com.
- Input PWRDWN: LVCMOS.
- Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2.
- External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input.
- Operates at AVDD = 2.5V for core circuit and internal PLL.
PI6CV857B Datasheet
