Datasheet4U Logo Datasheet4U.com

PI6CV857L - PLL Clock Driver

General Description

PI6CV857L PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels.

Key Features

  • • PLL clock distribution optimized for Double Data Rate SDRAM.

📥 Download Datasheet

Other Datasheets by Pericom Semiconductor (now Diodes Incorporated)

Part Number Description
PI6CV857B 1:10 PLL Clock Driver
PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory
PI6CV2304 160 MHz Clock Buffers
PI6CV304 160 MHz Clock Buffers
PI6CVF857 1:10 PLL Clock Driver
PI6C103 Precision Clock Synthesizer
PI6C106 Pentium/Pro System Clock Chip
PI6C18551 3.3V/5V 1 to 4 Clock Buffer
PI6C2405A Zero-Delay Clock Buffer
PI6C2408 3.3V 4+4 Ouptut Zero-delay Clock Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features • PLL clock distribution optimized for Double Data Rate SDRAM applications. • Distributes one differential clock input pair to ten differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Input PWRDWN: LVCMOS www.DataSheet4U.com • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.