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PI6C5930 - Low Skew CMOS PLL Clock Driver

General Description

The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs.

An internal loop filter eliminates the need for external compensation.

Key Features

  • Wide frequency range: 100 MHz max.
  • Five Q and one Q/2 outputs.
  • Output skew < 250ps (rising edges).
  • Internal RC loop filter network.
  • Low noise TTL-compatible outputs.
  • Balanced drive outputs: +24mA.
  • Outputs Hi-Z and registers reset when OE = LOW.
  • PLL bypass for testing and low-frequency.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C5930 Low Skew CMOS PLL Clock Driver Features • Wide frequency range: 100 MHz max.