PI6C5930 Description
The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs. An internal loop filter eliminates the need for external pensation. This driver generates six clock outputs:.
PI6C5930 Key Features
- Wide frequency range: 100 MHz max
- Five Q and one Q/2 outputs
- Output skew < 250ps (rising edges)
- Internal RC loop filter network
- Low noise TTL-patible outputs
- Balanced drive outputs: +24mA
- Outputs Hi-Z and registers reset when OE = LOW
- PLL bypass for testing and low-frequency