Datasheet Summary
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Low Skew CMOS PLL Clock Driver
Features
- Wide frequency range: 100 MHz max.
- Five Q and one Q/2 outputs
- Output skew < 250ps (rising edges)
- Internal RC loop filter network
- Low noise TTL-patible outputs
- Balanced drive outputs: +24mA
- Outputs Hi-Z and registers reset when OE = LOW
- PLL bypass for testing and low-frequency applications
- Small footprint 20-pin QSOP...