PI74SSTV16857 Datasheet | Pericom Semiconductor

Features • PI74 SSTV16857 is designed for low-voltage operation, VDD = VDDQ = 2.3V to 2.7V • Supports SSTL_2 Class I and II specifications • SSTL_2 Input and Output Levels • Designed for DDR Memory • Flow-Through Architecture • Package available: – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 173 mil wide plastic TVSOP (K) Product Description Peri Semiconductor’s PI74SSTV16857 series of logic circuits are produced using the pany’s advanced 0.35 micron CMOS technology, achieving industry leading speed. The 14-bit PI74SSTV16857 universal bus driver is designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET input which is LVCMOS. Data flow from D to Q is controlled by the differential clock , CLK, CLK and RESET. Data is triggered on the positive edge of CLK. CLK must be used to maintain noise margins. RESET must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock, are switched off. Logic Block Diagram CLK CLK RESET D1 V REF 38 39 34 48 35 R CLK Q1 Peri’s PI74SSTV16857 is characterized for operation from 0° to 70°C. TO 13 OTHER CHANNELS Product Pin Configuration Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK CLK VDD GND VREF RESET D8 D9 D10 D11 D12 VDD GND D13 D14 Product Pin Description Pin Name RESET CLK CLK D Q GND VDD VDDQ VREF Description Reset (Active Low) Clock Input Clock Input Data Input Data Output Ground Core Supply Voltage Output Supply Voltage Input Reference Voltage Inputs RESET L H Η H CLK X ↑ ↑ L or H CLK X ↓ ↓ L or H D X H L X Outputs Q L H L Q o(2) 48-Pin 40 A, K 39 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Truth Table(1) Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 Notes: 1. H =...