PI74SSTVF16859 Description
Peri Semiconductor’s PI74SSTVF16859 logic circuit is produced using the pany’s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are patible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II patible.
PI74SSTVF16859 Key Features
- Supports SSTL_2 Class I specifications on outputs
- All Inputs are SSTL_2 patible, except RESET which is LVCMOS
- Designed for DDR Memory
- Flow-Through Architecture
- Packages: 64-pin, 240-mil wide plastic TSSOP (A) 56-pin, Plastic Very Thin Fine Pitch Quad Flat No Lead QFN (ZB)