PI74SSTVF16857A Datasheet | Pericom Semiconductor

Features - Designed for low-voltage operation, 2.5V for PC1600 ~ PC2700; 2.6V for PC3200 - Supports SSTL_2 Class I output specifications - SSTL_2 Input and Output Levels - Designed for DDR Memory - Flow-Through Architecture - Packaging Options (Lead-free packages are available): - 48-pin 240 mil wide plastic TSSOP (A) - 48-pin 173 mil wide plastic TVSOP (K) Product Description Peri Semiconductor’s PI74SSTVF16857A series of logic circuits are produced using the pany’s advanced sub-micron CMOS technology, achieving industry leading speed. The 14-bit PI74SSTVF16857A universal bus driver is designed for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for the RESET input which is LVCMOS. Data flow from D to Q is controlled by the differential clock , CLK, CLK and RESET. Data is triggered on the positive edge of CLK. CLK must be used to maintain noise margins. RESET must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock, are switched off. R CLK Logic Block Diagram CLK CLK RESET D1 VREF 38 39 34 48 35 Q1 Peri’s PI74SSTVF16857A is characterized for operation from 0° to 70°C. Product Pin Configuration TO 13 OTHER CHANNELS .. Product Pin Description Pin Name RESET CLK CLK D Q GND VDD VDDQ VREF Description Reset (Active Low) Clock Input Clock Input Data Input Data Output Ground Core Supply Voltage Output Supply Voltage Input Reference Voltage (1) Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK CLK VDD GND VREF RESET D8 D9 D10 D11 D12 VDD GND D13 D14 48-Pin 39 A, K 38 11 37 36 35 34 33 32 31 30 29 28 27 26 25 Truth Table RESET L H Η H Inputs CLK X ↑ ↑ L or H CLK X ↓ ↓ L or H D X H L X Outputs Q L H L Q o( 2 ) Q9 VDDQ...