PT7C4512 Overview
It is designed to replace crystal oscillators in most electronic systems, clock multipliers and frequency translation devices with low output jitter. The device implements a standard fundamental mode using PLL techniques and inexpensive crystal to produce output clocks up to 200 MHz. The internal Logic divider is to generate nine different popular multiplication factors, allowing one chip to 1 X1/ICLK 2 Vcc 3 GND X2...
PT7C4512 Key Features
- Zero ppm multiplication error
- Input crystal frequency of 5
- 40 MHz
- Input clock frequency of 4
- 50 MHz
- Output clock frequencies up to 200 MHz
- Low period jitter 80ps (100~200MHz)
- Duty cycle of 45/55% of output clock up to 160MHz
- 9 selectable frequencies controlled by S0, S1 pins
- Operating voltages of 3.0 to 5.5V