74F256 Datasheet | Philips Semiconductors

FEATURES - bines dual demultiplexer and 8-bit latch - Serial-to-parallel capability - Output from each storage bit available - Random (addressable) data entry - Easily expandable - mon reset input - Useful as dual 1-of-4 active High decoder DESCRIPTION The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data inputs, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs. PIN CONFIGURATION A0 1 A1 2 Da 3 Q0a 4 Q1a 5 Q2a 6 Q3a 7 GND 8 16 V CC 15 MR 14 E 13 Db 12 Q3b 11 Q2b 10 Q1b 9 Q0b SF00805 TYPE TYPICAL PROPAGATION DELAY 7.0ns TYPICAL SUPPLY CURRENT (TOTAL) 28m A ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F256N N74F256D PKG DWG # 16-pin plastic DIP 16-pin plastic SO SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Da, Db A0, A1 E MR Q0a - Q3a Port A, port B inputs Address inputs Enable (active Low) Master Reset inputs (active Low) Port A outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A 1.0m A/20m A Q0b - Q3b Port B outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low...