74F256 Overview
The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states.
74F256 Key Features
- bines dual demultiplexer and 8-bit latch
- Serial-to-parallel capability
- Output from each storage bit available
- Random (addressable) data entry
- Easily expandable
- mon reset input
- Useful as dual 1-of-4 active High decoder