Philips 74F256
The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states.| Part No. | 74F256 |
|---|---|
| Datasheet | 74F256 Download |
| Manufacturer |  Philips |
| Description | Dual addressable latch |
| Buy | Stock & Price |
FEATURES
● Combines dual demultiplexer and 8-bit latch● Serial-to-parallel capability
● Output from each storage bit available
● Random (addressable) data entry
● Easily expandable
● Common reset input
● Useful as dual 1-of-4 active High decoder
DESCRIPTION
In the addressable latch mode, data at the Data inputs is written into the addressed latches. In the memory mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the dual 1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data inputs, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs. PIN CONFIGURATION A0 1 A1 2 Da 3 Q0a 4 Q1a 5 Q2a 6 Q3a 7 GND 8 16 V CC 15 MR 14 E 13 Db 12 Q3b 11 Q2b 10 Q1b 9 Q0b SF00805 TYPE TYPICAL P...
