74F259 Datasheet | Philips Semiconductors

FEATURES - bines demultiplexer and 8-bit latch - Serial-to-parallel capability - Output from each storage bit available - Random (addressable) data entry - Easily expandable - mon reset input - Useful as 1-of-8 active-High decoder DESCRIPTION The 74F259 addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. The addressed latches will follow the Data input with all unaddressed latches remaining in their previous states. In the store mode, all latches remain in their previous states and are unaffected by the Data or Address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held High (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode (MR=E=Low), addressed outputs will follow the level of the Data input, with all other outputs Low. In the Master Reset mode, all outputs are Low and unaffected by the Address and Data inputs. PIN CONFIGURATION A0 1 A1 2 A2 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 8 16 V CC 15 MR 14 E 13 D 12 Q7 11 Q6 10 Q5 9 Q4 SF00823 TYPE TYPICAL PROPAGATION DELAY 7.5ns TYPICAL SUPPLY CURRENT (TOTAL) 31m A ORDERING INFORMATION ORDER CODE DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F259N N74F259D PKG DWG # 16-pin plastic DIP 16-pin plastic SO SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D A0, A1, A2 E MR Data input Address inputs Enable input (active Low) Master Reset inputs (active Low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 1.0m A/20m A Q0 - Q7 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. 1989 Apr 11 853- 0362 06316 Philips Semiconductors Product specification Lat...