74F604 Datasheet | Philips Semiconductors

FEATURES - High impedance NPN base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION LE SELECT A/B A0 B0 A1 B1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A4 B4 A5 B5 A6 B6 A7 B7 Q7 Q6 Q5 Q4 Q0 - Stores 16-bit- wide Data inputs, multiplexed 8-bit outputs - 3-State outputs - Power supply current 75m A typical DESCRIPTION The 74F604 multiplexed latch is ideal for storing data from two input buses, A or B, and providing data from either the A or B latches to the output bus. Organized as 8-bit A and B latches, the latch outputs are connected by pairs to eight 2-input multiplexers. A Select (SELECT A/B) input determines whether the A or B latch contents are multiplexed to the eight 3-State outputs. Data entered from the B inputs are selected when SELECT A/B is Low; data from the A inputs are selected when SELECT A/B is High. Data enters the latches when the Latch Enable (LE) input is Low and is latched on the LE rising edge. The outputs are enabled when LE is High and disabled when LE is Low. A2 B2 A3 B3 Q3 Q2 Q1 GND SF01115 TYPE 74F604 TYPICAL PROPAGATION DELAY 7.5ns TYPICAL SUPPLY CURRENT (TOTAL) 75m A ORDERING INFORMATION DESCRIPTION 28-pin plastic DIP 28-pin plastic SOL MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F604N N74F604D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0- A7, B0- B7 SELECT A/B LE Q0- Q7 Data inputs Select input Latch Enable input (active Low) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 150/40 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 3m A/24m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. 1990 Mar 01 853- 0029 98991 Philips Semiconductors Product specification Dual octal latch (3-State) LOGIC SYMBOL 3 4 5 6 7 8 9 10 27 26 25 24 23 22 21 20 IEC/IEEE SYMBOL (IEEE/IEC) 2 1 G2 E1 EN 3 4 5 6 7 8 9 10 27 26 25 24 23 22 21 20 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7...