74F621 Datasheet | Philips Semiconductors

FEATURES - High-impedance NPN base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION OEAB 1 20 19 18 17 16 15 14 13 12 11 VCC OEBA B0 B1 B2 B3 B4 B5 B6 B7 - Octal bidirectional bus interface - Open collector outputs sink 64m A - Non-inverting DESCRIPTION The 74F621 is an octal transceiver featuring non-inverting open collector bus-patible outputs in both send and receive directions. The outputs are capable of sinking 64m A, providing very good capacitive drive characteristics. This octal bus transceiver is designed for asynchronous two-way munication between data buses. The control function implementation allows for maximum flexibility in timing. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the Enable inputs (OEBA and OEAB). The Enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the 74F621 the capability to store data by the simultaneous enabling of OEBA and OEAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of the bus lines are at high impedance, both sets of bus lines (16 in all) will remain in their last states. A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 GND 10 SF01135 TYPE 74F621 TYPICAL PROPAGATION DELAY 8.0ns TYPICAL SUPPLY CURRENT (TOTAL) 105m A ORDERING INFORMATION DESCRIPTION 20-pin plastic DIP 20-pin plastic SOL MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F621N N74F621D PKG DWG # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS A0 - A7, B0 - B7 OEBA, OEAB A0 - A7 B0 - B7 Data inputs Output Enable inputs Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 OC/40 OC/106.7 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA OC/24m A OC/64m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the...