74F786 Datasheet | Philips Semiconductors

FEATURES - Arbitrates between 4 asynchronous inputs - Separate grant output for each input - mon output enable - On board 4 input AND gate - Metastable- free outputs - Industrial temperature range available (- 40°C to +85°C) DESCRIPTION The 74F786 is an asynchronous 4- bit arbiter designed for high speed real- time applications. The priority of arbitration is determined on a first- e first- served basis. Separate bus grant (BGn) outputs are available to indicate which one of the request inputs is served by the arbitration logic. All BGn outputs are enabled by a mon enable (EN) pin. In order to generate a bus request signal a separate 4 input AND gate is provided which may also be used as an independent AND gate. Unused bus request (BR) inputs may be disabled by tying them high. The 74F786 is designed so that contention between two or more request signals will not glitch or display a metastable condition. In this situation an increase in the BRn to BGn t PHL may be observed. A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5µsec. Where: h = Typical propagation delay through the device and t and To are device parameters derived from test results and can most nearly be defined as: t = A function of the rate at which a latch in a metastable state resolves that condition. To = A function of the measurement of the propensity of a latch to enter a metastable state. To is also a very strong function of the normal propagation delay of the device. For further information, please refer to the 74F786 application notes. TYPICAL SUPPLY CURRENT (TOTAL) 55m A TYPE 74F786 TYPICAL PROPAGATION DELAY 6.6ns ORDERING INFORMATION ORDER CODE DESCRIPTION 16- pin plastic DIP 16- pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F786N N74F786D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = - 40°C to +85°C I74F786N I74F786D PKG DWG # SOT 38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS BR0 - BR3 A, B, C, D EN YOUT BG0 - BG3 DESCRIPTION Bus request inputs (active low)...