74HCT390
74HCT390 is Dual decade ripple counter manufactured by Philips Semiconductors.
FEATURES
- Two BCD decade or bi-quinary counters
- One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100
- Two master reset inputs to clear each decade counter individually
- Output capability: standard
- ICC category: MSI GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT390 are dual 4-bit decade ripple counters divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT390 decade or bi-quinary configuration, since they share a mon master reset input (n MR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clocks (n CP0 and n CP1 ) of each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100. Each section is triggered by the HIGH-to-LOW transition of the clock inputs (n CP0 and n CP1 ). For BCD decade operation, the n Q0 output is connected to the n CP1 input of, the divide-by-5 section. For bi-quinary decade operation, the n Q3 output is connected to the n CP0 input and n Q0 bees the decade output. The master reset inputs (1MR and 2MR) are active HIGH asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A HIGH level on the n MR input overrides the clocks and sets the four outputs LOW.
TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay n CP0 to n Q0 n CP1 to n Q1 n CP1 to n Q2 n CP1 to n Q3 n MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency...
