PZ5128
Overview
- Industry’s first TotalCMOS™ PLD - both CMOS design and process technologies
- Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed
- IEEE 1149.1-compliant, JTAG Testing Capability - 4 pin JTAG interface (TCK, TMS, TDI, TDO) - IEEE 1149.1 TAP Controller - JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ
- 5 Volt, In-System Programmable (ISP) using the JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms
- High speed pin-to-pin delays of 7.5ns
- Ultra-low static power of less than 100µA
- Dynamic power that is 70% lower at 50MHz than competing devices
- 100% routable with 100% utilization while all pins and all macrocells are fixed
- Deterministic timing model that is extremely simple to use
- 4 clocks with programmable polarity at every macrocell
