SAA4992H Datasheet | Philips Semiconductors

FEATURES - Digital data slicer - Acquisition and decoding of VPS data (EBU PDC System A) - Acquisition and decoding of Teletext packet 8/30/2 data (EBU PDC System B) - Separate storage of VPS data and packet 8/30/2 allowing dual standard PDC decoders - I2C-bus interface with automatic word address increment - Programmable interrupt for data received - Programmable error level detection - Single +5 V power supply. GENERAL DESCRIPTION The SAA5233 is a dual standard Program Delivery Control (PDC) decoder, allowing the reception and decoding of both VPS data (EBU PDC System A) and Teletext packet 8/30/2 data (EBU PDC System B). It is intended for use in European video recorders which are manually programmed, so that they receive broadcast real time switching signals for accurate timing of program recording. QUICK REFERENCE DATA SYMBOL VDD IDD fclk Vsync Vvid(p-p) Tamb Tstg supply voltage supply current crystal input frequency CVBS sync voltage amplitude CVBS video voltage amplitude (peak-to-peak value) operating ambient temperature storage temperature PARAMETER 4.5 - - 0.1 0.7 - 20 - 55 MIN. 5.0 30 27 0.3 1.0 - - TYP. 5.5 45 - 0.6 1.4 +70 +125 MAX. SAA5233 UNIT V m A MHz V V °C °C ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA5233P SAA5233T 16 20 PIN POSITION DIP16 SO20L MATERIAL plastic plastic CODE SOT38-1 SOT163-1 June 1994 Philips Semiconductors Objective specification Dual standard PDC decoder BLOCK DIAGRAM SAA5233 SCL handbook, full pagewidth SDA 13 I2 C BUS INTERFACE MEMORY INTERFACE AND RAM INTERRUPT CONTROL SAA5233 VDD V SS1 V SS2 V SS3 V SS4 V SS5 4 TELETEXT AND VPS CONTROL 8/30/2 ACQUISITION AND DECODING 9 10 11 16 DATA SLICER AND CLOCK REGENERATOR POWER ON RESET 13.5 MHz 27 MHz 1.125 MHz 27 MHz OSCILLATOR AND DIVIDER 6 7 8 ANALOGUE TO DIGITAL CONVERTER INPUT CLAMP AND SYNC SEPARATOR 1 2 3 MLB725 VPS ACQUISITION AND...