PHY6252
PHY6252 is Bluetooth 5.2 SOC manufactured by Phyplus.
Features
- High-performance low-power 32-bit processor
- Memory
- 512/256KB SPI NOR flash memory
- 64KB SRAM, all programmable retention in sleep mode
- 4-way instruction cache with 8KB Cache
- 96KB ROM
- 256bit efuse
- 19 general purpose I/O pins
- GPIO status retention in off/sleep mode
- configurable as serial interface and programmable IO MUX function mapping
- All pins can be configured for wake-up
- All pins for triggering interrupt
- 3 quadrature decoder(QDEC)
- 6-channel PWM
- 2-channel PDM/I2C/SPI/UART
- 4-channel DMA
- DMIC/AMIC with microphone bias
- 5-channel 12bit ADC with low noise voice PGA
- 6-channel 32bit timer, one watchdog timer
- Real timer counter (RTC)
- Power, clock, reset controller
- Flexible power management
- Operating Voltage range 1.8V to 3.6V
- Battery monitor
- Power consumption
- 0.3u A @ OFF Mode (IO wake up only)
- 1u A @ Sleep Mode with 32KHz RTC
- 13u A @ Sleep Mode with 32KHz RTC and all SRAM retention
- Receive mode: 8m A @3.3V power supply
- Transmit mode: 8.6m A (0d Bm output power) @3.3V power supply
- MCU: <90u A/MHz
- RC oscillator hardware calibrations
- Internal High/Low frequency RC osc
- 32KHz RC osc for RTC with +/-500ppm accuracy
- 32MHz RC osc for HCLK with 3% accuracy
- High Speed Throughput
- Support BLE 2Mbps Protocol
- Support Data Length...
