ASM2P5T905A Description
The ASM2P5T905A 2.5V single data rate (SDR) Clock buffer is a user-selectable single-ended or differential input Block Diagram TxS to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR Clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The ASM2P5T905A can...
ASM2P5T905A Key Features
- Guaranteed Low Skew < 25pS (max)
- Very low duty cycle distortion
- High speed propagation delay < 2.5nS. (max)
- Up to 250MHz operation
- Very low CMOS power levels
- 1.5V VDDQ for HSTL interface
- Hot insertable and Over-voltage tolerant inputs
- 3 level inputs for selectable interface
- Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
- Selectable differential or single-ended inputs and