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November 2006 rev 0.2
ASM2P5T905A
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Features
• Guaranteed Low Skew < 25pS (max) • Very low duty cycle distortion • High speed propagation delay < 2.5nS. (max) • Up to 250MHz operation • Very low CMOS power levels • 1.5V VDDQ for HSTL interface • Hot insertable and Over-voltage tolerant inputs • 3 level inputs for selectable interface • Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
LVEPECL input interface • Selectable differential or single-ended inputs and
five single ended outputs • 2.5V Supply Voltage • Available in TSSOP Package
Functional Description
The ASM2P5T905A 2.