HYB18T512161BF Description
HYB18T 512161 B F 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS pliant Internet Data Sheet Rev. 1.43 Internet Data Sheet .. HYB18T512161BF 20/22/25/28/33 512-Mbit Double-Data-Rate-Two SDRAM HYB18T512161BF Revision History:.
HYB18T512161BF Key Features
- mands entered on each positive clock edge, data and
- 1.8 V ± 0.1V VDD for [-25/-28/-33]
- 2.0 V ± 0.1V VDD for [-20/-22] data mask are referenced to both edges of DQS
- 1.8 V ± 0.1V VDDQ for [-25/-28/-33]
- Data masks (DM) for write data
- 2.0 V ± 0.1V VDDQ for [-20/-22]
- Posted CAS by programmable additive latency for better
- DRAM organizations with 16 data in/outputs mand and data bus efficiency
- Double Data Rate architecture
- Off-Chip-Driver impedance adjustment (OCD) and On- two data transfers per clock cycle Die-Termination (ODT) for better s