HYB18T512161BF - 512-Mbit x16 DDR2 SDRAM

latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

• The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
• Commands entered on each positive clock edge, data and.
• 1.8 V ± 0.1V VDD for [.
• 25/.
• 28/.
• 33].
• 2.0 V ± 0.1V VDD for [.
• 20/.
• 22] data mask are referenced to both edges of DQS.
• 1.8 V ± 0.1V VDDQ for [.
• 25/.
• 28/.
• 33].
• Data masks (DM) for write data.
• 2.0 V ± 0.1V VDDQ for [.
• 20/.
• 22].
• Posted C.