HYB18T512161BF
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and describes its main characteristics.
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features
:
- mands entered on each positive clock edge, data and
- 1.8 V ± 0.1V VDD for [- 25/- 28/- 33]
- 2.0 V ± 0.1V VDD for [- 20/- 22] data mask are referenced to both edges of DQS
- 1.8 V ± 0.1V VDDQ for [- 25/- 28/- 33]
- Data masks (DM) for write data
- 2.0 V ± 0.1V VDDQ for [- 20/- 22]
- Posted CAS by programmable additive latency for better
- DRAM organizations with 16 data in/outputs mand and data bus efficiency
- Double Data Rate architecture:
- Off-Chip-Driver impedance adjustment (OCD) and On- two data transfers per clock cycle Die-Termination (ODT) for better signal quality.
- four internal banks for concurrent operation
- Auto-Precharge operation for read and write bursts
- Programmable CAS Latency: 3, 4, 5, 6, 7
- Auto-Refresh,...
