HYB18T512160BF Key Features
- Off-Chip-Driver impedance adjustment (OCD) and On- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O Die-Te
- DRAM organizations with 4 and 8 data in/outputs
- Auto-Precharge operation for read and write bursts
- Double-Data-Rate-Two architecture: two data transfers
- Auto-Refresh, Self-Refresh and power saving Powerper clock cycle four internal banks for concurrent operation Down modes
- Programmable CAS Latency: 3, 4, 5 and 6
- Average Refresh Period 7.8 µs at a TCASE lower than
- Programmable Burst Length: 4 and 8 85 °C, 3.9 µs between 85 °C and 95 °C
- Differential clock inputs (CK and CK)
- Programmable self refresh rate via EMRS2 setting
