HYI18T256160B
HYI18T256160B is 256-Mbit Double-Data-Rate-Two SDRAM manufactured by Qimonda.
Overview
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
Features
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features
:
- Off-Chip-Driver impedance adjustment (OCD) and
- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O On-Die-Termination (ODT) for better signal quality
- DRAM organizations with 4, 8 and 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Double Data Rate architecture: two data transfers per
- Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes
- Programmable CAS Latency: 3, 4, 5 and 6
- Average Refresh Period 7.8 μs at a TCASE lower than
- Programmable Burst Length: 4 and 8 85 °C, 3.9 μs between 85 °C and 95 °C
- Differential clock inputs (CK and CK)
- Programmable self refresh rate via EMRS2 setting
- Programmable partial array refresh via EMRS2 settings
- Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read
- DCC enabling via EMRS2 setting
- Full and reduced Strength Data-Output Drivers data and center-aligned with write data.
- 1K page size
- DLL aligns DQ and DQS transitions with clock
- Packages: P(G)-TFBGA-60 for ×4 & ×8 ponents,
- DQS can be disabled for single-ended data strobe operation P(G)-TFBGA-84 for ×16 ponents
- Ro HS pliant Products1)
- mands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
- All Speed grades faster than DDR2- 400 ply with DDR2- 400 timing specifications when run at a clock rate
- Data masks (DM) for write data
- Posted CAS by programmable additive latency for better of 200 MHz. mand and data bus efficiency
TABLE 1
Performance Tables for
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