HYI18T256400B Overview
July 2007 HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) .. 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS pliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM HY[B/I]18T256400B[C/F](L), HY[B/I]18T256800B[C/F](L), HY[B/I]18T256160B[C/F](L) Revision History:.
HYI18T256400B Key Features
- Off-Chip-Driver impedance adjustment (OCD) and
- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O On-Die-Termination (ODT) for better signal quality
- DRAM organizations with 4, 8 and 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes
- Programmable CAS Latency: 3, 4, 5 and 6
- Average Refresh Period 7.8 μs at a TCASE lower than
- Programmable Burst Length: 4 and 8 85 °C, 3.9 μs between 85 °C and 95 °C
- Differential clock inputs (CK and CK)
- Programmable self refresh rate via EMRS2 setting