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HYI18TC256160AF - 256-Mbit Double-Data-Rate-Two SDRAM

General Description

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK rising and CK falling).

Key Features

  • The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:.
  • Off-Chip-Driver impedance adjustment (OCD) and.
  • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality.
  • DRAM organizations with 8,16 data in/outputs.
  • Auto-Precharge operation for read and write bursts.
  • Double Data Rate architecture: two data transfers per.
  • Auto-Refresh, Self-Refresh and power saving Powerc.

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Datasheet Details

Part number HYI18TC256160AF
Manufacturer Qimonda
File Size 3.45 MB
Description 256-Mbit Double-Data-Rate-Two SDRAM
Datasheet download datasheet HYI18TC256160AF Datasheet

Full PDF Text Transcription for HYI18TC256160AF (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HYI18TC256160AF. For precise diagrams, and layout, please refer to the original PDF.

November 2007 www.DataSheet4U.com HYB18T C25680 0 AF HYB18T C25616 0 AF HYI18TC256800AF HYI18TC256160AF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Prod...

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0AF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.3 Date: 2007-11-23 Internet Data Sheet HY[B/I]18TC256[80/16]0AF 256-Mbit Double-Data-Rate-Two SDRAM Revision History: Rev. 1.3, 2007-11 All All 98 www.DataSheet4U.com Adapted internet edition Added more products Corrected tRP in tables in chapter 7.2 Previous Revision: Rev. 1.2, 2007-04 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a refer

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