HYI18TC256800AF Datasheet | Qimonda

Overview This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. Features The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features : - Off-Chip-Driver impedance adjustment (OCD) and - 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O On-Die-Termination (ODT) for better signal quality - DRAM organizations with 8,16 data in/outputs - Auto-Precharge operation for read and write bursts - Double Data Rate architecture: two data transfers per - Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes - Programmable CAS Latency: 3, 4, 5 and 6 - Average Refresh Period 7.8 μs at a TCASE lower - Programmable Burst Length: 4 and 8 than 85 °C, 3.9 μs between 85 °C and 95 °C - Differential clock inputs (CK and CK) - Programmable self refresh rate via EMRS2 setting - Programmable partial array refresh via EMRS2 settings - Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read - DCC enabling via EMRS2 setting - Full and reduced Strength Data-Output Drivers data and center-aligned with write data. - 1KB page size - DLL aligns DQ and DQS transitions with clock - Packages: PG-TFBGA-84, PG-TFBGA-60 - DQS can be disabled for single-ended data strobe operation - Ro HS pliant Products1) - mands entered on each positive clock edge, data and - All Speed grades faster than DDR2- 400 ply with data mask are referenced to both edges of DQS DDR2- 400 timing specifications when run at a clock rate - Data masks (DM) for write data of 200 MHz. - Posted CAS by programmable additive latency for better mand and data bus efficiency 1) Ro HS pliant Product: Restriction of the use of certain hazardous substances (Ro HS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These...