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QL16X24B - Very-High-Speed CMOS FPGA

Features

  • Total of 122 I/O pins.
  • 114 Bidirectional Input/Output pins.
  • 6 Dedicated Input/High-Drive pins.
  • 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks Input + logic cell + output delays under 6 ns Chip-to-chip operating frequencies up to 110 MHz Internal state machine frequencies up to 150 MHz Clock skew < 0.5 ns Input hysteresis provides high noise immunity Built-in scan path permits 100% factory testing of logic and I/O cells and functional test.

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Datasheet preview – QL16X24B

Datasheet Details

Part number QL16X24B
Manufacturer QuickLogic
File Size 683.90 KB
Description Very-High-Speed CMOS FPGA
Datasheet download datasheet QL16X24B Datasheet
Additional preview pages of the QL16X24B datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com QL16x24B pASIC® 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS Very High Speed – ViaLink® metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density – A 16-by-24 array of 384 logic cells provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin CQFP packages. Low-Power, High-Output Drive – Standby current typically 2 mA. A 16-bit counter operating at 100 MHz consumes less than 50 mA.
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